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LT3952 1 3952fb for more information www.linear.com/LT3952 typical application features description 60v led driver with 4a switch current the lt ? 3952 is a current mode step-up dc/dc converter with an internal, 60v, 80m dmos power switch. the LT3952 is specifically designed to drive high power leds in multiple configurations. it combines input and output current regulation loops with output voltage regulation to operate as a flexible current/voltage source. programmable switching frequency with optional spread- spectrum modulation provides emi reduction, while still allowing optimization of the external components for efficiency or component size. the led current is program - mable with an external sense resistor, and can be adjusted from zero to full scale with a voltage at the ctrl pin. the external pwm input provides led on/off control and 4000: 1 dimming ratio, and an internal pwm generator delivers the efficiency of pwm dimming to standalone or i/o limited applications. the LT3952 is available in the thermally enhanced 28-lead tssop package. applications n 4000:1 true color pwm? dimming n 4a, 60v internal dmos switch n wide input voltage range: 3v to 42v n 0v to 60v output current regulation with monitor n pmos switch driver for pwm and output disconnect n led short-circuit protection and shortled flag n internal spread spectrum frequency modulation n constant-current and constant-voltage regulation n input current limit and monitor n adjustable frequency: 200khz to 3mhz, synchronizable to an external clock n 10:1 analog dimming n programmable open-led protection with openled flag n programmable v in undervoltage and overvoltage lockout n available in a 28-lead tssop package n display backlighting n automotive and avionic lighting n accurate current-limited voltage regulators l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and true color pwm is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including, 7199560, 7321203, 7746300. patents pending ivinp LT3952 v in v c shortled openled shortled openled sync/sprd intv cc tg isn isp fb gnd intv cc 750m en/uvlo ovlo ctrl v ref pwm ismon dim ivincomp rt ss 2.2f 3952 ta01a 100nf 2.2f 100v 2 1f 8.2nf 90.9k 1mhz 21.5k 100k 100k intv cc pwm ismon 1m 3.6k ivinn 4a input limit 15m 10h sw 4.7f v in 7v to 42v 16 led (50v) 333ma 57v open led regulation short-circuit robust boost led driver with spread spectrum frequency modulation v in (v) 0 efficiency (%) 3952 ta01b 50 20 40 10 30 100 90 70 80 60 ssfm off ssfm on efficiency vs input voltage
LT3952 2 3952fb for more information www.linear.com/LT3952 pin configuration absolute maximum ratings v in , ivinp, ivinn, shortled , openled , en/uvlo .................................................................. 42 v ovlo ........................................................................ 12 v sw, isp, isn, tg ....................................................... 60v i vinp-ivinn .....................................................? 1v to 3v ctrl, fb, dim, sync/sprd, pwm ......... in tv cc + 0.3v vc, ss, ismon, ivincomp ......................................... 3v rt, v ref ..................................................................... 2v int v cc (note 4) .......................................................3 .6v operating junction temperature range (notes 2, 3) lt3 952 e/ LT3952 i .............................. ? 40 c to 125 c lt3 952 h ............................................ ? 40 c to 150 c storage temperature range .................. ? 65 c to 150 c lead temperature (soldering, 10 sec) ................... 30 0 c (note 1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view fe package 28-lead plastic tssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 gnd sw sw sw ivinn ivinp v in en/uvlo ovlo intv cc sync/sprd gnd vc rt gnd isp isn tg ismon ivincomp openled shortled pwm ss v ref ctrl fb dim 29 gnd ja = 30c/w exposed pad (pin 29) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range LT3952efe#pbf LT3952efe#trpbf LT3952fe 28-lead plastic tssop ?40c to 125c LT3952ife#pbf LT3952ife#trpbf LT3952fe 28-lead plastic tssop ?40c to 125c LT3952hfe#pbf LT3952hfe#trpbf LT3952fe 28-lead plastic tssop ?40c to 150c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix
LT3952 3 3952fb for more information www.linear.com/LT3952 electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = ivinp = ivinn = 12v, isp = isn = 24v, en/uvlo = pwm = 3v, ctrl = 2v, ovlo = 0v unless otherwise noted parameter conditions min typ max units minimum operating voltage 3 v supply current fb = 1.3v, r t = 40.2k, ctrl = 0v en/uvlo = 0v, ctrl = 0v en/uvlo = 1.15v, ctrl = 0v 1.5 0 35 2.2 1 60 ma a a internal regulator intv cc output voltage ctrl = 0v 2.90 3.00 3.10 v intv cc dropout voltage v in = 3v, ctrl = 0v 150 mv intv cc undervoltage lockout intv cc rising, ctrl = 0v 2.62 2.68 2.74 v intv cc uvlo hysteresis ctrl = 0v 200 mv reference voltage output v ref voltage i vref = ?100a , ctrl = 0v l 1.955 2.000 2.045 v v ref line regulation 3v < v in < 42v , ctrl = 0v 0.01 %/v v ref load regulation 0a < i vref < ?100a , ctrl = 0v 0.6 % current feedback ctrl range for current sense threshold adjustment 0.2 1.2 v ctrl pwm shutdown threshold ctrl falling 100 125 mv ctrl pwm threshold hysteresis 12.5 mv ctrl zero-scale offset 200 mv ctrl input bias current ctrl = 0v, current out of pin 20 100 na current sense common mode input range ctrl = 1.5v 0 60 v full-scale current sense accuracy (v isp -v isn ) isp = 60v, ctrl = 1.5v l 245 250 255 mv midrange current sense accuracy (v isp -v isn ) isp = 60v, ctrl = 0.7v 115 125 135 mv 1/10th scale current sense accuracy (v isp -v isn ) isp = 60v, ctrl = 0.3v 10 25 40 mv low side current sense accuracy (v isp -v isn ) isp = 0v, ctrl = 1.5v l 240 250 260 mv overcurrent sense threshold l 350 375 390 mv isp to vc transconductance ctrl = 1.5v 275 s isp/isn input bias current pwm = 5v (active), isp = 60v pwm = 0v (standby), isp = 60v 250 0 0.1 a a current sense monitor ratio (v ismon )/(v isp -v isn ) ctrl = 0.4v, 0.8v 4 v/v current sense monitor accuracy (v ismon ) ctrl = 1.5v , isp = 60v 0.950 1.000 1.050 v input current sense amplifier amplifier supply current (from ivinp) ivinp = ivinn = 42v 35 60 a i vin regulation threshold (v ivinp-ivinn ) l 55 60 65 mv i vincomp to vc transconductance 1650 s input common mode minimum voltage 3 v ivinp/ivinn to monitor voltage gain v ivinp-ivinn = 30mv 20 v/v
LT3952 4 3952fb for more information www.linear.com/LT3952 electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = ivinp = ivinn = 12v, isp = isn = 24v, en/uvlo = pwm = 3v, ctrl = 2v, ovlo = 0v unless otherwise noted parameter conditions min typ max units tg gate driver pwm input high threshold pwm rising l 1.15 1.2 1.25 v pwm hysteresis 20 mv tg on voltage v isp-tg , v isp > 10v 7.5 9.5 v tg off voltage v isp-tg , pwm = 0v 0 0.3 v tg turn-on time c load = 470pf, pwm rising 100 ns tg turn-off time c load = 470pf, pwm falling 150 ns output voltage feedback fb voltage regulation threshold (v fb ) ctrl = 1.5v l 1.188 1.182 1.200 1.200 1.212 1.218 v v fb open-led threshold fb rising v fb ? 65mv v fb ? 45mv v fb ? 25mv v fb open-led threshold hysteresis 15 mv fb overvoltage threshold fb rising v fb + 15mv v fb + 30mv v fb + 40mv v fb overvoltage threshold hysteresis 15 mv fb pin bias current l 20 100 na feedback line regulation 3v < v in < 42v 0.0003 %/v fb to vc transconductance 450 s vc output impedance 5000 k soft-start soft-start sourcing current current out of pin, ss = 0.1v 18 25 37 a soft-start sinking current ss = 1.8v 1.5 2.5 4.1 a soft-start hiccup retry threshold 200 mv soft-start strong pull-down on-resistance 120 oscillator rt voltage 1.20 v switching frequency r t = 470k r t = 90.9k r t = 40.2k r t = 25.5k l 180 0.95 1.90 2.75 215 1.0 2.0 3.0 250 1.05 2.10 3.25 khz mhz mhz mhz maximum duty cycle r t = 470k sync = 300khz clock signal, r t = 470k r t = 90.9k r t = 40.2k r t = 25.5k l 98 97 92 85 99 98 95 90 80 % % % % % minimum off-time 50 ns minimum on-time 75 ns sync/sprd pin resistance to gnd v sync = 2v 100 k sync/sprd input high threshold 1.5 v sync/sprd input low threshold 0.4 v spread spectrum minimum step as percentage of f sw 1 % spread spectrum maximum step as percentage of f sw 31 %
LT3952 5 3952fb for more information www.linear.com/LT3952 electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = ivinp = ivinn = 12v, isp = isn = 24v, en/uvlo = pwm = 3v, ctrl = 2v, ovlo = 0v unless otherwise noted parameter conditions min typ max units pwm generator pwm pin pull-up/pull-down current pwm = 1.2v, dim = 0.7v l 5 10 15 a pwm generator lower threshold offset 0.2v < dim < 1.2v v dim ? 15 v dim + 0 v dim + 15 mv pwm generator upper threshold offset 0.2v < dim < 1.2v v dim + 825 v dim + 950 v dim + 1075 mv pwm generator frequency dim = 0.7v, c pwm = 22nf 230 hz dim pin output current dim = 0.7v l 10 20 30 a tg duty cycle using pwm generator dim = 0.345v dim = 0.535v dim = 0.725v dim = 1.105v 1 21 42.5 86 10 30 50 90 21 39 57.5 94 % % % % power switch switch on-resistance i sw = 500ma 80 m switch leakage current sw = 60v, ctrl = 0v 2 a vc to current threshold transconductance 7.5 s maximum power switch current limit vc = 2v 4 4.5 5 a logic inputs/outputs en/uvlo disable threshold en/uvlo falling l 1.191 1.230 1.269 v en/uvlo threshold internal hysteresis 75 mv en/uvlo hysteresis current en/uvlo = 1.25v, device in shutdown en/uvlo = 1.5v, device in operation 2 0 0.4 a a ovlo threshold ovlo rising l 1.191 1.230 1.269 v ovlo threshold hysteresis 25 mv ovlo input bias current ovlo = 1v 15 100 na shortled on-resistance i shortled = 1ma 60 shortled output low voltage i shortled = 2ma 0.3 v shortled off-state leakage shortled = 42v 1 a openled on-resistance i openled = 1ma 60 openled output low voltage i openled = 2ma 0.3 v openled off-state leakage openled = 42v 1 a note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LT3952e is guaranteed to meet specified performance from 0c to 125c. specifications over the ?40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the LT3952i is guaranteed to meet performance specifications over the ?40c to 125c operating junction temperature range. the LT3952h is guaranteed to meet performance specifications over the full ?40c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes. operating lifetime is derated at junction temperatures greater than 125c. note 3: the LT3952 includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed the maximum operating junction temperature when overtemperature is active. continuous operating above the specified maximum operating junction temperature may impair device reliability. note 4: intv cc is an output and is not meant to be externally driven.
LT3952 6 3952fb for more information www.linear.com/LT3952 typical performance characteristics intv cc voltage vs temperature intv cc dropout vs load and temperature shutdown current vs temperature en/uvlo bias current above threshold intv cc vs input voltage intv cc vs input voltage, dropout quiescent current vs input voltage en/uvlo thresholds vs temperature en/uvlo hysteresis current vs temperature temperature (c) ?50 0 supply current (a) 10 20 30 40 50 60 v en = 1.15v 0 50 100 150 3952 g01 temperature (c) ?50 1.10 threshold (v) 1.15 1.20 1.25 1.30 1.35 1.40 en/uvlo rising en/uvlo falling 0 50 100 150 3952 g02 temperature (c) ?50 current (a) 1.75 2.00 150 3952 g03 1.50 1.25 0 50 100 2.25 v en = 1.25v en/uvlo voltage (v) 2 en/uvlo current (a) 1.00 ?0.80 0.80 0.40 0.00 ?0.40 0.60 0.20 ?0.20 ?0.60 ?1.00 32 3925 g04 42 22 12 v in (v) 0 quiescent current (ma) 1 1.25 1.5 40 3952 g05 0.75 0.5 0 10 20 30 0.25 2 1.75 temperature (c) ?50 2.90 intv cc (v) 2.95 3.00 3.05 0 50 3952 g06 100 150 v in (v) 0 intv cc (v) 2.75 3.00 3.25 40 3952 g07 2.50 2.00 10 20 30 2.25 3.50 v in (v) 1.5 2.00 intv cc (v) 2.25 2.50 2.75 3.00 3.25 3.50 2 2.5 3 3.5 3952 g08 4 intv cc (v) v in (v) load (ma) 0 intv cc dropout (v) 0.3 0.4 0.5 12 3952 g09 0.2 0.1 0 3 6 9 15 v in = 2.9v 150c 25c ?50c
LT3952 7 3952fb for more information www.linear.com/LT3952 typical performance characteristics fb thresholds vs temperature switching frequency vs temperature switching frequency vs r t sw current limit vs temperature isp/isn full-scale threshold vs temperature isp/isn mid-scale threshold (ctrl = 0.7v) vs temperature intv cc current limit vs temperature v ref voltage vs temperature reference voltage vs input voltage temperature (c) ?50 0 intv cc current limit (ma) 5 10 15 20 25 30 normal: intv cc = 2.5v foldback: intv cc = 0v 0 50 100 150 3952 g10 temperature (c) ?50 v ref (v) 2.000 2.025 150 3952 g11 1.975 1.950 0 50 100 2.050 i ref = 100a v in (v) 0 v ref (v) 2.00 2.02 2.04 40 3952 g12 1.98 1.96 1.92 10 20 30 1.94 2.08 2.06 temperature (c) ?50 1.12 fb thresholds (v) 1.14 1.16 1.18 1.20 1.22 1.24 0 50 100 150 3952 g13 ov fb rising ov fb falling v fb openled rising openled falling r t (k) 10 0.1 switching frequency (mhz) 1 10 100 1000 3952 g14 temperature (c) ?50 switching frequency (mhz) 1.000 1.025 150 3952 g15 0.975 0.950 0 50 100 1.050 r t = 90.9k temperature (c) ?50 sw current limit (a) 4.4 4.6 150 3952 g16 4.2 4.0 0 50 100 5.0 4.8 temperature (c) ?55 isp-isn (mv) 250 251 252 150 3952 g17 249 248 246 0 50 100 247 254 ctrl = 2v v isp = 60v 253 temperature (c) ?50 122 isp-isn (mv) 123 124 125 126 127 128 0 50 100 150 3952 g18
LT3952 8 3952fb for more information www.linear.com/LT3952 typical performance characteristics v isp-isn threshold vs fb voltage v isp-isn threshold vs ctrl isp-isn threshold vs output voltage tg rise/fall time vs capacitance tg driver turn-on tg driver turn-off isp/isn 1/10th scale threshold (ctrl = 0.3v) vs temperature isp/isn overcurrent threshold vs temperature ismon voltage vs isp-isn voltage temperature (c) ?50 22 isp-isn (mv) 23 24 25 26 27 28 0 50 100 150 3952 g19 temperature (c) ?50 isp/isn overcurrent threshold (mv) 375 385 150 3952 g20 365 355 0 50 100 395 isp-isn (mv) 0 0 ismon (v) 0.2 0.4 0.6 0.8 1.0 1.2 50 100 150 200 3952 g21 250 fb (v) 1.1 0 isp-isn (mv) 50 100 150 200 250 300 1.15 1.2 1.25 1.3 3952 g22 v ctrl = 2v v out (v) 0 245.0 isp-isn (mv) 247.5 250.0 252.5 255.0 10 20 30 40 3952 g23 50 60 ctrl (v) 0 0 isp-isn (mv) 50 100 150 200 250 300 0.5 1 1.5 2 3952 g24 c load (nf) 0 t rise/fall (ns) 500 600 700 10 3952 g25 400 300 200 0 2.5 5 7.5 100 900 t rise (ns) t fall (ns) 800 pwm 2v/div tg 5v/div 200ns/div 3952 g26 pmos: vishay siliconix si7309 pwm 2v/div tg 5v/div 3952 g27 200ns/div pmos: vishay siliconix si7309
LT3952 9 3952fb for more information www.linear.com/LT3952 typical performance characteristics pwm generator duty cycle vs dim voltage pwm generator currents vs temperature pwm generator frequency vs pwm capacitor pwm generator thresholds vs temperature pwm generator operation and step ivinp-ivinn threshold vs temperature ivincomp vs ivinn-ivinp ovlo thresholds vs temperature 10ms/div pwm 0.5v/div dim 0.5v/div i led 200ma/div 3952 g35 1.2v pwm threshold ivinp-ivinn (mv) 0 ivincomp (v) 0.8 1.2 80 3952 g29 0.4 0 20 40 60 1.6 temperature (c) ?50 ivinp-ivinn (mv) 58 60 150 3954 g28 56 54 0 50 100 64 62 temperature (c) ?50 1.125 ovlo thresholds (v) 1.150 1.175 1.200 1.225 1.250 1.275 ovlo rising ovlo falling 0 50 100 150 3952 g30 dim voltage (v) 0 pwm generator duty cycle (%) 40 60 2 3952 g31 20 0 0.5 1 1.5 120 100 80 pwm capacitor (nf) pwm frequency (hz) 10000 1000 100 10 1 0 100 1000 10 3952 g32 temperature (c) ?50 current (a) 5 10 15 150 3952 g33 0 ?5 ?15 0 50 100 ?10 25 20 dim pullup current pwm pullup current pwm pulldown current temperature (c) ?50 threshold (v) 0.8 1.2 150 3952 g34 0.4 0 0 50 100 1.6 0.6 1 0.2 1.4 dim = 0.5v upper threshold lower threshold
LT3952 10 3952fb for more information www.linear.com/LT3952 pin functions gnd (1, 12, 28, exposed pad pin 29): ground pins. the exposed pad of the LT3952 acts as both gnd and heat sink. it must be connected to a large copper area for proper operation. sw (pins 2, 3, 4): switch pins. minimize copper area at these pins to increase efficiency and reduce emi. ivinn (pin 5): input current sense amplifier negative input. the input current sense amplifier reduces the switching current in the case of an overload. vc is reduced when the ivinp-ivinn voltage exceeds the 60mv built-in potential. tie ivinp-ivinn across an external sense resistor to set auxiliary current limit. if unused, tie to v in . ivinp (pin 6): auxiliary current sense amplifier posi - tive input. also acts as the bias supply for the amplifier to provide a function independent from the v in pin. the ivinp/ivinn amplifier can operate from voltages either above or below v in . tie this pin to the positive terminal of a sense resistor, and do not use resistance in series with this pin. if unused, tie to v in . v in (pin 7): input supply pin. bypass this pin with a ca - pacitor to gnd as close to the ic as possible. en/uvlo (pin 8): master enable and v in undervoltage lockout. when low, the ic is put into shutdown mode and the q current is reduced to <1a. this pin utilizes a 1.23v comparator with hysteresis, as well as a hysteresis current source for programming additional hysteresis externally. drive with a digital signal greater than 1.5v for simple on/off control. tie to a resistor divider between v in and gnd to set an external uvlo threshold. ovlo (pin 9): overvoltage lock out comparator. this pin disables switching and tg in the case of an overvoltage. this pin utilizes a 1.23v comparator with hysteresis. when the voltage at ovlo exceeds the threshold, the switching is disabled until the voltage at ovlo falls 25mv below the threshold. tie to gnd if unused. intv cc (pin 10): internal low dropout regulator output. intv cc is regulated to 3v, and must be bypassed with an external capacitor of at least 2.2f . intv cc is the power supply for the internal dmos gate driver and control circuitry. users may apply <5ma loads to intv cc . over - loading intv cc can cause unintentional device shutdown from intv cc falling below the 2.68v uvlo threshold. sync/sprd (pin 11): frequency synchronization and spread spectrum enable pin. tie low for fixed internal clock, tie to intv cc for spread spectrum internal clock, or drive with an external clock for frequency synchronization with no spread spectrum. when using an external clock for frequency synchronization, r t resistor should be chosen to program a switching frequency 20% lower than the sync pulse frequency. synchronization (switch turn-on) occurs 50ns after the rising edge of sync. vc (pin 13): g m amplifier output for external loop compensation. stabilize the loop with a c or series rc network. this pin is set to a high impedance state during pwm dimming off-time. rt (pin 14) : switching frequency adjustment pin. set switching frequency using a resistor to gnd (see typical performance characteristics for values). for sync func - tion, set the frequency 20% slower than the sync pulse frequency . do not leave this pin open. pcb layout must have this component close to the ic. dim (pin 15): pwm generator control voltage. this pin outputs a fixed 20a current, and controls a triangle wave generator on the pwm pin to determine the pwm duty cycle. 0.2v to 1.2v range on dim adjusts pwm duty from 0% to 100%. float this pin or tie to intv cc if unused, tie a resistor from dim to gnd to set a fixed voltage, or apply an external voltage to dim for adjustable pwm duty cycle. fb (pin 16) : output voltage loop feedback pin. connect to a resistor divider from v out . in constant-voltage ap- plications, fb sets the output voltage. in constant-current applications, the fb divider is set higher than the expected output voltage to act as open-led protection. as the volt - age at fb rises to within 45mv of the regulation point, the openled flag is asserted if the output current also falls below one-tenth the full-scale value. if the fb voltage exceeds the regulation point by 30mv, the switching is terminated and the tg pin pulls high in order to discon - nect the led load.
LT3952 11 3952fb for more information www.linear.com/LT3952 pin functions ctrl (pin 17): output current sense adjust pin. sets voltage regulation threshold across isp/isn current sense resistor. 0.2v to 1.2v range on ctrl adjusts isp/isn threshold from 0mv to 250mv . tie to v ref or intv cc for fixed 250mv threshold. below 100mv, the ctrl pin acts as an auxiliary pwm input for combination pwm/analog dimming on a single pin. v ref (pin 18): reference voltage output. this pin outputs a fixed 2v reference, and supplies up to 100a for use in generating a reference voltage for the ctrl pin. when using a resistor divider, bypass this pin with 100nf to gnd. ss (pin 19): soft-start and hiccup control pin. this pin modulates oscillator frequency and vc voltage clamp when it is below 1.7v. a capacitor on the pin sets the soft-start interval as well as hiccup retry timing in fault mode. the ss pin has a 25a pull-up current in normal mode, a 2.5a pull-down current in hiccup mode, and a 120 pull-down resistance in start-up mode. optional latchoff mode is set with a 750k pull-up resistor from intv cc to ss. pwm (pin 20) : on/off control. used for tg on/off control and pwm dimming of the led. logic low idles regulator to a lower q current, makes the tg pin drive to i sp level, and makes the vc pin high impedance. logic high turns on error amplifier, enables switching and tg. the pwm threshold is 1.2v . tie to v ref or intv cc for continuous operation. the pwm pin also supplies 10a switched current sources to generate a triangle wave on external capacitor for the pwm dimming generator. it is safe to overdrive these currents with an external signal. shortled (pin 21): open-drain short-circuit indicator. shortled pulls low in the case of an led overcurrent fault, and releases during the start-up phase of the next soft-start cycle. the state of shortled is only updated when the pwm pin is high. tie this pin to desired logic high voltage with an external resistor. the maximum recommended sink current is 2ma to limit excess power dissipation. leave the pin open if unused. openled (pin 22): open-drain open-led indicator. openled pulls low when the voltage at the fb pin is within 45mv of the regulation point and the led current has dropped to 10% of the full-scale output. openled releases when the fb voltage falls below the threshold. the state of openled is only updated when the pwm pin is high. tie this pin to desired logic high voltage with an external resistor. the maximum recommended sink current is 2ma to limit excess power dissipation. leave the pin open if unused. ivincomp (pin 23): auxiliary current sense amplifier monitor output. the voltage at ivincomp is a 20 ampli - fied and buffered version of the ivinp-ivinn differential voltage, and the vc voltage will be reduced when ivin - comp reaches its 1.2v threshold. a 1f capacitor to gnd is suggested to filter inductor ripple and compensate the input current loop. during p wm dimming, the ivincomp pin stores the input current regulation loop value on the capacitor during the pwm off time. do not load this pin. if the input current regulation loop is not used, this pin may be connected to gnd. ismon (pin 24): output current monitor pin. the volt - age at ismon is a 4 amplified and buffered version of the isp , isn differential voltage. during pwm dimming, the ismon voltage continues to reflect the instantaneous output current, falling during the pwm low time. tg (pin 25): top gate driver output. an inverted and level- shifted version of the pwm input signal. drives the gate of an external pmos transistor between v isp and v isp ? 7.5v to provide load-side on/off control, pwm dimming, and fault mode disconnect. leave tg unconnected if not used. isn (pin 26): output current sense amplifier negative input. connect this pin to the load side of the output cur - rent sense resistor. if unused, tie to output voltage. isp (pin 27) : output current sense amplifier positive input. also serves as the positive rail for the tg driver. limit impedance in series with this pin.if unused, tie to output voltage.
LT3952 12 3952fb for more information www.linear.com/LT3952 block diagram 1.23v 1.155v ? ++ + ? + ? + ? 26 27 ? + ? + ? + ? + ? + ? + ? + ? + ? + ? + 0.3v pwm 1.2v 0.1v 1.2v vmode fbov ledoc x4 ? + x20 0.375v isn 24 ismon 18 v ref intv cc 140a 2v 13 2, 3, 4 14 vc sw 0.1v ocp 22m 3952 bd isp 17 ctrl 16 fb 5 ivinn 6 ivinp 7 v in intv cc uv ctrpwm ss c/10 0.2v ? + 1.23v shdn 2a ? + ldo osc + ssfm ssfm off tsd (165c) ss/flt shdn 2.5a 25a ledoc tsd fbov s r q g pwmon qd pwmon c/10 vmode tsd intv cc 1.2v ss rt gnd 11 sync/sprd 19 ss 10 ivincomp 23 en/uvlo 8 ? + 1.23v ovshdn ovlo 9 shortled 21 x1 ? + openled 22 q ledoc ovp otp pwm r s ? + + uv ssfm on ? + + ? ? + ? + r 950mv intv cc 10a intv cc 20a 1.2v ctrpwm pwmon isp isp ? 7.5v 10a dim s q q 15 pwm 20 tg 25 1, 12, 28, 29
LT3952 13 3952fb for more information www.linear.com/LT3952 operation the LT3952 is a fixed-frequency, current mode boost con - verter with a feature set ideal for driving high power led lamps. it provides input and output current regulation, as well as output voltage regulation and fault handling. the operation of the LT3952 is best understood by referring to the block diagram. in normal operation, with the pwm pin low, the switching is disabled, the tg pin is pulled high to isp to turn off the pmos disconnect switch, the vc pin is high impedance to store the previous switching state on the external compensation capacitor, and the isp/isn pin bias currents are reduced to leakage levels. when the pwm pin transitions high, the tg pin transitions low after a short delay. at the same time, the internal os - cillator wakes up and generates a pulse to set the pwm latch, turning on the internal nmos power switch. the switch current is sensed and added to a stabilizing slope compensation ramp, and the resultant signal is compared to the vc voltage. the inductor current increases linearly during the switch on-time. when the current sense signal exceeds the vc value, the latch is reset and the internal nmos power switch is turned off. during the switch off-time, energy is transferred from the inductor and the inductor current decreases. at the completion of each oscillator cycle, internal signals such as slope compensa - tion return to their starting points and a new cycle begins with the set pulse from the oscillator . through this repetitive action, the ic establishes a switch - ing duty cycle to regulate a current or voltage in the load. the vc signal is integrated over many switching cycles, and is an amplified version of the difference between the led current sense voltage, measured between isp and isn, and the target difference voltage set by the ctrl pin. in this manner, the error amplifier sets the correct peak switch current level to keep the led current in regulation. if the error amplifier output increases, more current is demanded in the switch; if it decreases, less current is demanded. if the switch current exceeds the internal 4.5a current limit, the latch is reset regardless of the state of the pwm comparator. likewise, in any fault condition ; i.e., fb overvoltage (v fb > 1.23v), led overcurrent (v isp-isn > 375mv), overvoltage lockout or intv cc undervoltage the switching is immediately disabled. in addition to the v isp-isn to ctrl feedback loop, the LT3952 also provides additional loops to control input current and output voltage. the loops are connected in a wired-or configuration, where the auxiliary loops are only allowed to reduce the value of vc in the event that one or more exceeds its threshold. this means that even if one or more of the auxiliary loops is below its regulation point, vc will not rise unless the output (led) current sense is also below its regulation point. the first auxiliary loop is the output voltage feedback loop using the fb pin. it is typically used to prevent the output voltage from exceeding a safe value. the voltage at the fb pin is compared to an internal reference voltage of 1.2v, and the amplified difference pulls down the vc pin in the case that fb exceeds 1.2v. as vc drops, the switching current reduces and in this manner the output voltage is regulated so that fb = 1.2v.
LT3952 14 3952fb for more information www.linear.com/LT3952 operation the second auxiliary loop is the input current limit us - ing the ivinn, ivinp, and ivincomp pins. similar to the output (led) current loop, the input current is sensed as the differential voltage across a sense resistor. as the average ivinp/ivinn differential voltage exceeds 60mv, ivincomp reaches its 1.2v threshold, and vc is reduced in order to limit the input current to the 60mv threshold. intv cc bypass capacitor intv cc is the internal power supply for the ic, and sup- plies the gate drive to the internal power switch. a bypass capacitor is required from intv cc to gnd for stability and filtering of the switching noise. for best results, use a ceramic capacitor of 2.2f or greater, and place the capacitor as close to the ic as possible. v ref bypass capacitor v ref is the 2v reference output and can be bypassed with 100nf to gnd. for best results, place the bypass capacitor close to the ic and away from the noisy switching nodes. programming the turn-on/turn-off thresholds with the en/uvlo pin the LT3952 provides an adjustable v in undervoltage lock - out (uvlo) function using the en/uvlo pin. the en/uvlo function provides a precision 1.23v falling threshold with 75mv internal hysteresis as well as a 2a pull-down current in the off state to provide additional, user-programmable hysteresis. this pin can also be driven with a logic level greater than 1.5v or tied to v in for always-on operation. in order to program an external uvlo, tie the en/uvlo pin to a resistor divider between v in and gnd. the divider ratio determines the baseline turn-off/turn-on thresholds and the value of the upper resistor determines the ad - ditional hysteresis. v in en/uvlo r1 r2 LT3952 3952 f01 figure 1 the most important (and precise) threshold is the turn- off threshold from v in falling. the following equations determine the resistor values: v uv(falling) = 1.23 ? 1 + r1 r2 ? ? ? ? ? ? v uv(rising) = 1.305 ? 1 + r1 r2 ? ? ? ? ? ? + 2a ? r1 for example, a 12v falling uvlo with roughly 10% total hysteresis requires 185k for r1. the closest standard value is 187k, therefore: r1 = 187k r2 = 21.5k v uv(falling) = 11.93v v uv(rising) = 13.03v
LT3952 15 3952fb for more information www.linear.com/LT3952 operation programming the overvoltage disable with the ovlo pin it is also possible to program a disable threshold if the input voltage rises too high. the ovlo pin has a 1.23v comparator with 25mv internal hysteresis. if the voltage at ovlo exceeds the 1.23v threshold, the switching is disabled, tg pulls high, and the ss pin pulls low. the device begins a new soft-start sequence when the voltage at ovlo has fallen 25mv below the threshold. although it is possible to connect this pin with an indepen - dent resistor divider, the component count is minimized by splitting the bottom resistance of the standard en/uvlo divider to generate an additional tap point. continuing the previous equation, the desired value of r3 is 8k for an ovlo threshold of 32v. subtract this from the previous value of r2 in order to find the value of r2a. in our case, r3 = 8.06k and the closest 1% resistor for the new r2a value is 13.3k. the thresholds are recalculated if desired from the expanded divider ratios: v uv(falling) = 1.23 ? 1 + r1 r2a + r3 ? ? ? ? ? ? v uv(rising) = 1.305 ? 1 + r1 r2a + r3 ? ? ? ? ? ? + 2a ? r 1 v ov(rising) = 1.23 ? 1 + r1 + r2a r3 ? ? ? ? ? ? v ov(falling) = 1.205 ? 1 + r1 + r2a r3 ? ? ? ? ? ? in our example: r1 = 187k, r2a = 13.3k, r3 = 8.06k v uv(falling) = 11.998v v uv(rising) = 13.104v v ov(rising) = 31.796v v ov(falling) = 31.151v figure 2 v in en/uvlo r1 r2a r3 LT3952 0vlo 3952 f02 using the previous values of r1 and r2 from the uvlo section, the new r3 value is computed using the desired rising threshold by: r3 = 1.23 ? r1 + r2 v ov(rising) ? ? ? ? ? ? the middle resistor will be designated r2 a. to obtain the value for r2a, subtract the calculated value of r3 from the old r2 value.
LT3952 16 3952fb for more information www.linear.com/LT3952 operation led current control and monitor the led current is programmed through the combination of an external sense resistor and a voltage on the ctrl pin. the ctrl voltage adjusts the setpoint of the current sense amplifier on the isp and isn pins from 0mv to 250mv, and the external sense resistor defines the output current for a given setpoint. the current sense resistor is typically placed at the top of the led strand, although the rail-to-rail isp/isn inputs allow placement at the bottom of the strand as well. the required ctrl voltage for a desired analog setpoint is computed by: v ctrl = 0.2 + 4 ? v isp-isn as the ctrl voltage nears 1.2v , a crossover from adjustable threshold to a precision internal 250mv setpoint takes place and some nonlinearity occurs as shown in the isp-isn vs ctrl graph in the typical performance characteristics. it is therefore desirable to drive the ctrl pin well above 1.2v when the 250mv setpoint is desired. tying ctrl to the 2v v ref output is an excellent method of doing so. led current monitoring the ismon pin provides a buffered output representing the differential voltage on isp-isn for current monitoring applications. the normal working range of ismon is from 0v to 1v, and the gain from isp-isn to ismon is 4. this corresponds to a 1v output at ismon when the isp-isn differential voltage has reached the 250mv maximum. isp r led sensed current LT3952 isn 3952 f03 figure 3 figure 4 the required sense resistor for a desired output current is computed by: r led = v isp-isn i out in the case of the fixed 250mv setpoint: r led = 0.25 i out for example, a 500ma output requires a 0.5 sense resis - tor when using the fixed 250mv setpoint. in adjustable mode, the working range of ctrl is from 0.2v to 1.2v and adjusts the setpoint of isp and isn from 0mv to 250mv. in this manner, analog dimming is achieved. ctrl (v) 0 0 isp-isn (mv) 50 100 150 200 250 300 0.5 1 1.5 2 3952 f04
LT3952 17 3952fb for more information www.linear.com/LT3952 operation external pwm dimming the pwm pin, in combination with an external pmos transistor driven from the tg pin, allows on/off control and pwm dimming of the led current. the pwm pin has a fixed 1.2v threshold, and driving pwm higher than 1.2v enables the device for switching and causes the tg pin to drive to a level roughly 7.5v lower than the voltage at isp. during the low time of pwm, the tg pin is driven to the voltage at isp to turn off the external pmos, and the LT3952 is put into a low power standby state. switching and the error amplifiers are disabled and the vc pin is three-stated to preserve the value of vc voltage for accelerated start-up upon the next rising edge of pwm. the ctrl pin also offers a pwm function to allow analog and digital dimming on a single pin. below 0.1v on ctrl, the device is also put into standby mode with sw, tg, and the error amplifiers disabled. keep in mind that between 0.2v and 0.1v on ctrl, the device is not disabled, although the output current is commanded to 0. the value of vc reduces towards the minimum, and tg keeps the output pmos enabled, which discharges the output through the led lamps. for effective pwm dimming using the ctrl pin, please ensure that the low voltage on ctrl is below 0.1v. this is easily obtained using an external open-drain device to pull down a resistor divider used to generate the ctrl setpoint. alternately, enabling and disabling a dac output driving ctrl also gives excellent results. internal pwm generator the pwm pin can also provide a self-oscillating pwm generator for standalone operation by simply tying a small capacitor from pwm to gnd. in this configuration, 10a pwm v dim + 950mv v dim dim 20a LT3952 3952 f05 figure 5 pull-up and pull-down current sources generate a triangle waveform on the pwm pin whose peak and valley points are defined by the voltage on the dim pin and whose frequency is defined by the external capacitor. v pwm-valley = v dim v pwm-peak = v dim + 950mv f pwm = 5200 c pwm (f) figure 6. lower dim voltage figure 7. higher dim voltage 1.2v v dim 3952 f06 v pwm 1.2v v dim v pwm 3952 f07 by raising and lowering the voltage on the dim pin, the triangle wave intersects the 1.2v pwm threshold at dif - ferent points, changing the pwm duty cycle.
LT3952 18 3952fb for more information www.linear.com/LT3952 operation as the dim pin exceeds 1.2v , the pwm duty cycle will be 100%. as the dim pin exceeds 2.3v , the internal pwm generator is disabled along with the switched 10a pull- down on pwm. the pwm pin will continue to be pulled to intv cc with the 10a pull-up current. for applications utilizing external pwm dimming, it is recommended to disable the internal pwm generator by floating the dim pin or tying it to intv cc . this will provide the fastest pwm response for high dimming ratios. programming the frequency of pwm dimming consists only of selecting the proper capacitor for the pwm pin according to: c nf () = 5200 f pwm hz () a common selection is 39nf for roughly 133hz. programming the pwm duty cycle consists of setting a voltage on the dim pin according to: v dim(v) = 0.95 ?duty + 0.25 as shown in figure 5, a single resistor in combination with the 20a output current of dim can be used to program the duty cycle. r dim(k ) = 47.5 ?duty + 12.5 for adjustable duty cycle control, an external voltage can be applied at the dim pin using a dac or external supply. to slowly increase the light output upon start-up or restart, a capacitor can also be used with the dim circuit. to fade from dark to full brightness, only a capacitor is required. to fade from dark to a fixed duty cycle, place a capacitor in parallel with the dim resistor. upon start-up or fault retry, an internal pull-down with 2k series resistance is applied to the dim pin to discharge any external capacitor before the start-up sequence begins. be aware that this will temporarily load an external voltage applied to dim. dim LT3952 dim LT3952 3952 f08 figure 8. fade on to full brightness, or to preset duty
LT3952 19 3952fb for more information www.linear.com/LT3952 figure 9 ivincomp ivinp ivinn r ivin sensed current LT3952 3952 f09 operation input current limit the LT3952 provides adjustable input current limiting through the ivinp/ivinn/ivincomp amplifier. connect the ivinp and ivinn sensing terminals across a resistor in series with the input. a 20x amplified version of the ivinp?ivinn differential is generated at ivincomp. a capacitor at ivincomp provides filtering and averaging of the input ripple. as the average ivinp?ivinn differential reaches 60mv, the ivincomp voltage will reach its 1.2v regulation threshold and the cycle-by-cycle switch current will be reduced. in this manner, the input current is regulated to 60mv differential between ivinp and ivinn. r sense m () = 60mv i in lim () a () for example, a 2.4a input current limit is programmed with a 25m sense resistor. be aware that input current on start-up and pwm dim - ming is larger than steady state due to the output current required to fill the output capacitor. it is recommended to set the input limit appropriately to prevent interruption of the regulated output. input current monitor an input current monitor is available as the voltage on ivincomp , which reflects a voltage equal to 20 the ivinp-ivinn differential voltage and has a working range of 0v to 1.2v as the ivinp-ivinn voltage varies from 0mv to 60mv. ivincomp is a high impedance output and should not be loaded. averaging of current sense ripple, and compensa - tion of the feedback loop is achieved using a 1f capacitor from ivincomp to gnd. output voltage regulation/limiting the LT3952 provides a voltage-feedback error amplifier through the fb pin to provide output voltage regulation and limiting for open-led protection. in the case of an open-led strand, the current commanded by ctrl is never achieved and the device continues to drive the output voltage higher. if left unchecked, this could result in overvoltage damage to the external components and the power switch itself, and therefore an output volt - age limit is required. by connecting fb to a resistor divider between v out and gnd, the maximum output voltage regulates at the 1.2v threshold of the fb pin. the maximum output voltage is computed as follows: v out v () = 1.2 ? 1 + r4 r5 ? ? ? ? ? ? figure 10 figure 11 ivinp ivinn r ivin c f lt r f lt LT3952 3952 f10 ivincomp v out fb r4 r5 LT3952 3952 f11 in some cases, such as deep discontinuous conduction, a large input ripple current may cause the input current limit to activate early, cutting into the typical regulation profile. in this situation, it is possible to filter the ripple down to a smoother level using an external rc network.
LT3952 20 3952fb for more information www.linear.com/LT3952 operation a simple method to determine the proper resistor values is to choose a value of r5 that draws a tolerable amount of current at the 1.2v regulation point, and to compute r4 by using: r4 = v out ? 1.2 () ? r5 1.2 for example, r5 = 24k draws 50a at the regulation point, and for a 24v output limit, the desired value of r4 is 456k. the closest standard value to this is 453k, providing 23.85v output voltage limit. it is necessary to set the regulation point slightly higher than the worst-case voltage drop of the leds to avoid cut-in of the voltage limit during normal regulation. open led flag and overvoltage protection the LT3952 provides an indicator of the open-led condition on the openled pin, as well as an internal overvoltage detection to prevent output overshoot if the led strand goes open under load. both of these features are based on the voltage at the fb pin. the openled pin consists of an open-drain nmos pull down to be connected with an external pull-up resistor to the user? s desired voltage. this pin tolerates up to 42v, and has a pull-down strength of 60. please be aware of power dissipation and keep the openled current to a few ma maximum. the openled pin pulls low when the following two condi - tions are met: 1. the voltage at fb rises to within 45mv of the 1.2v regulation point. 2. the output current is detected to be less than one-tenth of the value commanded by ctrl. the openled pin releases when the voltage at fb falls to 65mv below the 1.2v regulation point. this sequence prevents false openled flags from momentary overshoot. an overvoltage condition is detected by the voltage at fb rising to 30mv above the 1.2v regulation point. upon detection of an overvoltage condition, the switching is disabled and tg is pulled high to disconnect and protect the load. switching is re-enabled when the fb voltage falls by 15mv . an overvoltage condition does not affect the state of the openled pin. switching frequency the switching frequency is programmed with a resistor from the rt pin to gnd. the rt pin is regulated to 1.2v, and the output current of r t adjusts the oscillator frequency. r t LT3952 rt 3952 f12 figure 12
LT3952 21 3952fb for more information www.linear.com/LT3952 operation the overall switching period is defined by the sum of two parts: a fixed 50ns off-time that defines d max , and a variable time defined by the rt current. to determine the proper r t value for a desired switching frequency, using the following equation: r t k () = 88.9 f sw (mhz) 1.13 for example, a 2mhz switching frequency results in a desired r t resistance of 40.6k, which has 40.2k as the closest standard value. table 1 provides some commonly used values. table 1. switching frequency vs r t value f sw (mhz) r t (k) 3.0 25.5 2.0 40.2 1.0 90.9 0.4 243 0.215 470 frequency synchronization and spread spectrum the LT3952 sync pin acts as both an external clock input for frequency synchronization and the enable signal for internal spread spectrum feature. tie the sync/sprd pin low for fixed-frequency internal clock, tie to intv cc for spread-spectrum internal clock, or drive with an external clock for frequency synchronization with no internal spread spectrum. when synchronizing to an external clock, the r t resis- tor should be chosen to program a switching frequency 20% lower than the external clock frequency. even when synchronizing, a soft-start cycle will first start the oscil - lator in frequency foldback to minimize inrush current. as the soft-start cycle nears completion, the device will then transition to the external frequency. when the sync/sprd pin is tied high for greater than 32 clock cycles, the device will enable spread-spectrum clocking for emi reduction. by continuously varying the oscillator frequency, spread spectrum distributes the emi power generated during the switching cycle over a group of frequencies rather than concentrating it at a single frequency. therefore, the measured emi power at any single frequency is reduced compared to that of fixed- frequency operation. in spread-spectrum mode, the oscillator frequency is varied in a pseudorandom manner from the nominal frequency to 31% above nominal in 1% steps. this unidirectional adjustment allows LT3952 to avoid a sensitive band in the system simply by programming the nominal frequency slightly above it. the proportional step size allows the user to easily determine r t value for their specified emi test bin size, and the pseudorandom method provides tone suppression from the frequency variation itself.
LT3952 22 3952fb for more information www.linear.com/LT3952 operation the pseudorandom value is updated proportionally to the oscillator frequency, using a rate of f sw /32. this rate allows multiple passes of the entire group of frequencies during standard emi test dwell times. the maximum steady-state inductor current, i l(max) , should be less than 3a to allow for current ripple and transient response. the desired inductance is determined based on the steady-state current ripple. a typical rule of thumb is to set the inductor current ripple to a maximum of 25% of the switch current limit. boost: l boost v in(min) v led(max) ?v in(min) ( ) v led(max) ? 1a ? f sw buck: l buck v led(max) v in(min) ?v led(max) ( ) v in(min) ? 1a ? f sw buck-boost: l bb v in(min) ?v led(max) v led(max) + v in(min) ? ? ? ? ? ? f sw ? 1a table 2 provides some recommended inductor vendors. table 2. inductor manufacturers vendor web wurth elektronik www.we-online.com coilcraft www.coilcraft.com cooper www.cooperet.com figure 13. average conducted emi ? 1mhz amplitude (dbv) 3952 f14 ssfm off ssfm on 90 80 70 60 50 40 30 20 10 start 700khz res bw 9khz end 1.7mhz dwell time 10ms (250 hz) 0 vbw 90khz inductor selection inductor selection consists of two parameters: saturation current rating and inductance value. a higher switching frequency allows the use of a smaller inductance value at the expense of increased switching loss. the saturation current rating of the inductor is selected appropriately for the 4a current limit of the device. an approximation for maximum inductor current (efficiency = 100%) is based on the maximum led current and the input/output ratio: i l(max) a () = v led(max) v in(min) ? ? ? ? ? ? ?i led
LT3952 23 3952fb for more information www.linear.com/LT3952 operation output capacitor selection in the case of driving leds, their exponential current/ voltage characteristic dictates that output voltage ripple translates almost directly to led current ripple. although the effect is not visible to the eye, large led current ripple may affect the output current accuracy and color spectrum and it is therefore advisable to keep the output voltage ripple below a few percent. for the boost and buck-boost topologies, output cur - rent is delivered in pulses and the filtering requirement is higher than for the buck topology with its continuous ou tput current. assuming a low esr ceramic capacitor and 25% inductor current ripple, use the following equations to compute the required output capacitance for a desired output ripple voltage, ?v led . boost, buck-boost: c out = i led ?v led ?v in () v led ? ? v led ?f sw buck: c out = 0.3 ?i led 8? ? v led ?f sw input capacitor selection the input capacitor is also selected based on desired voltage ripple. complementary to output capacitor selec - tion, the discontinuous input current of the buck topology requires more filtering than the continuous input current of the boost or buck-boost. use the following equations to determine the input capacitance required for a desired input ripple voltage, ?v in . boost, buck-boost: c in = 0.3 ?i led ? v led v in 8? ? v in ?f sw buck: c in = v in ?i led ?v in ?v led () ? v in ?v in 2 ?f sw schottky rectifier selection the power schottky diode conducts the switching current during the switch off-time. select a diode rated for at least 1.5 ? i led to account for current variation from efficiency and inductor ripple. the reverse-breakdown voltage should be at least 20% greater than the maximum reverse voltage expected in circuit. loop compensation the LT3952 uses an internal transconductance error amplifier whose vc output compensates the control loop. the external inductor, output capacitor and the compen - sation resistor and capacitor determine the loop stability. the inductor and output capacitor are chosen based on per formance, size and cost. the compensation resistor and capacitor at vc are selected to optimize control loop response and stability. for typical led applications, a 6.8nf to 10nf compensation capacitor at vc is adequate, and a series resistor increases the slew rate on the vc pin to maintain tighter regulation of led current during fast transients on the input supply of the converter. external pmos disconnect/pwm switch a high side pmos disconnect switch with a minimum v th of ?2v is recommended in most LT3952 applications. this switch is enabled and disabled during pwm dimming, and disconnects the output in shutdown and during fault conditions. select a pmos transistor with a v ds rating greater than the open-led regulation voltage set by fb, and with a continuous current rating greater than i led . soft-start the LT3952 incorporates flexible soft-start and the option of hiccup or latchoff mode for customizing fault response. the ss pin provides a 25a pull-up current for charging, a 2.5a pull-down current for discharging, and a 120 nmos pull-down switch for clearing an external soft- start capacitor. the state of each of these components is determined by the soft-start/fault sequence, and will be described herein. shutdown mode: during shutdown mode, all ss cur - rents and the pull-down switch are disabled, effectively
LT3952 24 3952fb for more information www.linear.com/LT3952 operation three-stating the ss pin. this is to avoid sinking quiescent current in the case that an external resistor pull-up is connected to ss. when the device leaves shutdown mode, the nmos pull- down switch is activated to clear the voltage at the soft-start capacitor. the device waits in this state until the voltage at ss drops below 0.2v, and until start-up is enabled as defined by pwm > 1.2v and ctrl > 100mv. if both enable signals are already valid upon leaving shutdown mode, the nmos pull-down is activated for 10s longer than is required to pull the ss voltage below 0.2v. in all cases, this action provides a start-up profile where the initial voltage at ss can be considered approximately 0v. in the event that the device is shut down by en/uvlo or the intv cc voltage dropping below 2.68v, the ss pin initially goes high impedance and then restarts the clear, charge sequence as described. start-up mode: once start-up is enabled by pwm and ctrl both valid, the nmos pull-down switch is disabled and the 25a charging current is enabled. the voltage at ss begins ramping in a linear manner until it reaches 0.2v, at which point switching and the tg driver are enabled. from 0.2v to 1.7v on ss, the frequency and the current limit are increased linearly with ss voltage to provide a smooth start-up profile with low inrush current. the required soft-start capacitor for a desired start-up time is computed from the 1.5v range of ss and the 25a charge current. c ss (nf) = 16.67 ? t ss (ms) for example, a soft-start time of roughly 0.5ms is gener - ated with an 8.2nf capacitor. depending on output and load conditions the device may enter regulation before ss reaches 1.7v, however it is the combination of the 1.7v threshold and the sensing of at least one-tenth of the output current defined by ctrl that signifies the successful completion of soft-start. this becomes important when start-up is enabled by a low duty cycle pwm signal. the explanation is as follows: a low duty cycle pwm signal could cause excessive start-up times if it were allowed to interrupt the soft- start sequence. therefore, once start-up is initiated by pwm > 1.2v and ctrl > 150mv , it temporarily ignores a logical disable by either of those signals. the device continues to soft-start with switching and tg enabled until either the voltage at ss reaches the 1.7v level, or the output current reaches one-tenth of the full-scale value. at this point the device begins following the dimming control as designated by pwm or ctrl. if at any time an output overcurrent is detected, sw and tg will be disabled even as ss continues to charge. this will be discussed in further detail in the fault handling section. pwm 2v/div ss 2v/div sw 20v/div i led 200ma/div 3952 f15 normal pwm cycle output ready: latched startup ends latched startup begins 10ms/div figure 14. pwm latched startup one note is when pwm dimming using ctrl, the output current is commanded to zero during the low time of ctrl even as the soft-start voltage rises. fault handling: although the fault handling sequence may change based on the soft-start conditions, the switching is disabled and the tg driver immediately pulls high upon detection of an output overcurrent fault. this provides safe output disconnect even in the case of a dead short on the output. when an overcurrent is detected and tg and sw are disabled, ss is still required to charge to the 1.7v upper threshold before it begins discharging back down using the 2.5a current source. if ss is already at or above 1.7v, it begins discharging immediately upon the disable of tg and sw. if ss is still in the start-up phase when an output overcurrent fault is detected, then ss continues charging even as tg and sw are disabled. it charges to the 1.7v level before reversing direction and discharging to the 0.2v level with the 2.5a current source. this provides additional delay to allow the system to recover from the overcurrent condition.
LT3952 25 3952fb for more information www.linear.com/LT3952 operation once ss has discharged to the 0.2v level, the sequence of clearing ss with the 120 nmos pull-down and restarting the 25a charge phase reoccurs as previously described. switching and tg are not re-enabled until ss again climbs to the 0.2v threshold. if at this point an overcurrent is still detected, then sw and tg are again disabled as ss continues to climb to the 1.7v threshold before reversing direction. in this manner, a hiccup retry cycle is obtained with a maximum switching duty cycle of 10%, the ratio of 25a pull-up to 2.5a pull-down currents. this low hiccup duty cycle reduces input power during sustained overload conditions. 1.7v 0.2v 3952 f13 ss shortled figure 15. ss in sustained hiccup mode if a latched-off response is desired, a user simply sets a pull-up resistor from intv cc to ss with a value low enough to prevent ss from discharging to the 0.2v level. for the low pull-down current of 2.5a, even a relatively large value of 750k to intv cc prevents ss from reaching the automatic retry threshold and effectively provides a fault latchoff. at this point, a manual retry is obtained by entering and exiting shutdown mode, upon which the 120 nmos pull-down clears the ss voltage in preparation for retry. shortled flag: the LT3952 provides an open-drain shortled pin to flag the overcurrent detection. this pin is connected with a pull-up resistor to the user? s voltage (up to 42v), and has a pull-down strength of 60 . please be aware of power dissipation and keep the pull-up current to a few ma maximum. the shortled pull-down activates immediately upon detection of a fault and stays on throughout the charge/ discharge phase of the hiccup cycle. the pull-down releases as the ss capacitor is cleared to 0v during the restart phase and stays released as ss re-charges to the 0.2v retry threshold. if at this point a fault is again detected, the pin is again pulled down as the hiccup retry cycle continues. for the user detecting fault with an irq, this falling edge is used to count a desired number of faults before full system shutdown, or the rising edge is used to prepare the system for a new start-up cycle. board layout the high speed operation of the LT3952 demands careful attention to board layout and component placement. the exposed pad of the package is the gnd terminal of the ic and is also important for thermal management of the ic. it is crucial to achieve a good electrical and thermal contact between the exposed pad and the ground place of the board. to reduce electromagnetic interference (emi), it is important to minimize the area of the high dv/ dt switching node between the inductor, sw pins, and anode of the schottky rectifier. use a ground plane under the switching node to eliminate interplane coupling to sensitive signals. the length of the high di/dt trace from the sw pin through the schottky recti - fier and filter capacitor to gnd should be minimized, and the ic gnd pins should be connected to the large copper area beneath the ic. the gnd terminal of the int v cc capacitor should be placed near the gnd of the switching path. the ground for the v ref capacitor, the ivincomp capacitor, the compensation network, and other dc control signals should be star connected to the underside of the ic. do not route high impedance signals such as fb, dim, ivinn, rt and vc near the switching nodes, and minimize the length of their routes to avoid picking up switching noise. since there is a small, but variable, dc bias current on the isp/isn/ivinp/ivinn inputs, minimize resistance in series with these pins to avoid creating an offset. kelvin connecting these lines to the terminals of their respective sense resistors provides best performance.
LT3952 26 3952fb for more information www.linear.com/LT3952 typical applications short-circuit robust boost led driver with spread spectrum frequency modulation ivinp LT3952 v in v c shortled openled shortled openled sync/sprd intv cc tg isn isp fb gnd intv cc 750m m1 en/uvlo ovlo ctrl v ref pwm ismon dim ivincomp rt ss 2.2f 3952 ta02a 100nf r ss 750k opt 1f 8.2nf 90.9k 1mhz 21.5k 57v open led regulation 100k 100k intv cc pwm ismon 1m 3.6k ivinn 4a input limit 15m l1 10h d1 sw 4.7f v in 7v to 42v 16 led (50v) 333ma 2.2f 100v 2 d1: vishay vs-10bq060 l1: wurth we-lhmi74437349100 m1: vishay si7415dn i led 1a/div shortled 2v/div 3952 ta02b 100ms/div ss 2v/div v led 20v/div v in (v) 0 led current (ma) 3952 ta02d 50 20 40 10 30 350 345 335 325 340 330 320 37961 ta02c 100ms/div i led 1a/div shortled 2v/div ss 2v/div v led 20v/div frequency (mhz) 0 amplitude (dbv) 80 70 50 20 60 40 10 30 0 3952 ta02e 10 4 8 2 6 ssfm off ssfm on short led protection without r ss : hiccup mode led current vs input voltage short led protection with r ss : latchoff mode average conducted emi comparison
LT3952 27 3952fb for more information www.linear.com/LT3952 typical applications sepic led driver with input current limit ivinp LT3952 v in v c shortled openled shortled d1: vishay vs-10bq060 l1: wurth we-dd744874100 m1: vishay si7309dn openled sync/sprd intv cc tg isn isp fb gnd intv cc 620m en/uvlo ovlo ctrl v ref pwm ismon dim ivincomp rt ss 2.2f 3952 ta03a 100nf 4.7f 35v l1b 2.2f 100v d1 1f 10nf 90.9k 1mhz 49.9k 100k 39.2k 4.75k 100k 100k intv cc pwm ismon 1m 1k ivinn 3a input limit 20m ? ? l1a 10h sw 4.7f v in 5v to 35v 42v transient 4v uvlo falling 36.5v ovlo rising 6 led (17v) 400ma sepic efficiency vs input voltage led current vs input voltage v in (v) 0 led current (ma) 3952 ta03b 40 20 10 30 410 406 398 392 402 394 408 400 404 396 390 v in (v) 0 efficiency (%) 3952 ta03c 40 30 10 20 100 90 70 80 60
LT3952 28 3952fb for more information www.linear.com/LT3952 shortled 2v/div 3952 ta04e ss 1v/div v led 10v/div 20ms/div i led 50ma/div 3952 ta04d 400ns/div 1.67s 4000:1 2.22s 3000:1 3.33s 2000:1 pwm 1v/div 1.67s 1.67s 1.67s 4000:1 2.22s 2.22s 2.22s 3000:1 3000:1 3.33s 3.33s 3.33s 2000:1 2000:1 2000:1 led dead short response led current vs input voltage efficiency over working range high pwm dimming ratio typical applications 2mhz boost led driver with 4000:1 pwm dimming and overvoltage protection ivinp LT3952 v in v c shortled openled shortled d1: pmeg4010 l1: wurth we-lhmi 74437346033 m1: vishay si7309dn openled sync/sprd intv cc tg isn isp fb gnd intv cc 1.65 26v open led regulation en/uvlo ovlo ctrl v ref pwm ismon dim ivincomp rt ss 2.2f 3952 ta04a 8.2nf 4.7f 50v l1 3.3h 1f 10nf 37.4k 2.15mhz 12.1k 143k 24.3k 12.1k 100k 100k intv cc pwm ismon 249k 2.2k ivinn 3a input limit 20m sw 4.7f v in 7v to 16v 40v transient 6.1v uvlo falling 18.3v ovlo rising 8 led (22v) 150ma m1 d1 v in (v) 6 led current (ma) 3952 ta04b 18 14 1 08 12 16 154 152 150 153 149 151 148 v in (v) 6 efficiency (%) 3952 ta04c 18 14 1 08 12 16 100 90 70 80 60
LT3952 29 3952fb for more information www.linear.com/LT3952 typical applications 3mhz buck-boost led driver with internal pwm dimming and fade start ivinp LT3952 v in v c shortled openled shortled openled sync/sprd intv cc tg isn isp fb gnd intv cc 0.75 en/uvlo pwm ovlo ctrl v ref dim ivincomp rt ss 2.2f 3952 ta05a 100nf 1f 100v 1f 10nf 25.5k 3mhz 21.5k 1m 31.6k 100k 100k 75k intv cc 1m 2.4k d1: vishay vs-10bq060 l1: wurth we-lhmi74437346025 m1: vishay si7309dn ivinn 15m l1 2.5h sw 4.7f v in 5v to 35v 42v transient 39v ovlo rising 2.2f 0.25s fade 39nf 130hz 8 led 333ma d1 4.7f 50v 57v limit dim (v) 0 percent (%) 3952 ta05c 2.52 10.5 1.5 pwm duty cycle efficiency v in = 12v 100 60 20 80 40 0 v in (v) 0 efficiency (%) 3952 ta05b 3530 20 105 15 25 100 90 70 80 60 pwm duty cycle and efficiency vs dim voltage efficiency vs input voltage power on ? fade start 3952 ta05d pwm 1v/div v in 10v/div v led 10v/div i led 200ma/div 40ms/div
LT3952 30 3952fb for more information www.linear.com/LT3952 package description please refer to http://www.linear.com/product/LT3952#packaging for the most recent package drawings. fe28 (eb) tssop rev k 0913 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 34 5 6 7 8 9 10 11 12 13 14 192022 21 151618 17 9.60 ? 9.80* (.378 ? .386) 4.75 (.187) 2.74 (.108) 28 27 26 2524 23 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 0.195 ? 0.30 (.0077 ? .0118) typ 2 recommended solder pad layout exposed pad heat sink on bottom of package 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 4.75 (.187) 2.74 (.108) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 28-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663 rev k) exposed pad variation eb
LT3952 31 3952fb for more information www.linear.com/LT3952 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 01/16 replaced reference to note 5 to note 4 in absolute maximum table removed note 4 from intv cc dropout voltage specification replaced note 5 with note 4 clarified ss (pin 19) description ? replaced ?shutdown mode? with ?start-up mode? clarified the block diagram pin designators clarified figure 11 clarified open led flag and overvoltage section 60mv becomes 65mv clarifed led dead short response graph clarifed power on ? fade start graph clarifed related parts table 2 3 5 11 12 19 20 28 29 32 b 01/17 clarified t ypical application uvlo/ovlo 27
LT3952 32 3952fb for more information www.linear.com/LT3952 ? linear technology corporation 2015 lt 0117 rev b ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/LT3952 related parts typical application 3a buck mode led driver part number description comments lt3795 110v high side led controller with spread spectrum and boost short-circuit protection v in : 4.5v to 110v, v out(max) = 110v, pwm dimming = 3000:1, i sd < 10ma, tssop-28 package lt3518 2.3a, 2.5mhz high current led driver with 3000:1 dimming with pmos disconnect fet driver v in : 3v to 30v, v out(max) = 45v, 3000:1 pwm dimming, i sd < 1a, 4mm 4mm qfn-16 and tssop-16e packages lt3755/ lt3755-1/ lt3755-2 high side 40v, 1mhz led controllers with true color 3000:1 pwm dimming v in : 4.5v to 40v, v out(max) = 75v, 3000:1 pwm dimming, i sd < 1a, 3mm 3mm qfn-16 and msop-16e packages lt3956 high side 80v, 3.3a, 1mhz led driver with true color 3000:1 pwm dimming v in : 6v to 80v, v out(max) = 80v, pwm dimming = 3000:1, i sd < 1a, 5mm 6mm qfn-36 package lt3761 high side 80v, 1mhz led controller with 3000:1 pwm dimming and internal pwm generator v in : 4.5v to 60v, v out(max) = 80v, 3000:1 true color pwm dimming, analog, i sd <1a, msop-16e package lt3478/lt3478-1 4.5a, 2mhz high current led drivers with 3000:1 dimming v in : 2.8v to 36v, v out(max) = 40v, 3000:1 pwm dimming, i sd < 1a, tssop-16e package lt3954 high side 40v, 5a 1mhz led driver with 3000:1 pwm dimming and internal pwm generator v in : 4.5v to 40v, v out(max) = 40v, true color pwm dimming = 3000:1, analog, i sd < 1a, 5mm 6mm qfn-36 package LT3952 v in v c shortled openled shortled sync/sprd tg ivinp ivinn ivincomp isn en/uvlo ovlo intv cc ismon gnd sw fb ctrl v ref pwm dim rt ss 2 4.7f 50v 4.7f 50v 3952 ta06a 100nf 6.8nf d1: diodes, inc sbr3a40sa l1: wurth we-lhmi74437346047 m1: vishay si7309dn 90.9k 1mhz 78.7k 12.4k 100k intv cc pwm d1 m1 3 to 9 led (3v to 30v) 3a 220 82m l1 4.7h isp 1f 50v v in 12v to 40v 9.6v falling uvlo 2.2f efficiency vs v in led current vs input voltage v in (v) 10 efficiency (%) 3952 ta06c 40 30 20 100 90 70 80 60 3 led (30w) 5 led (50w) 7 led (70w) 9 led (90w) v in (v) 10 led current (a) 3952 ta06b 40 30 20 3.25 3.10 3.15 3.00 3.20 3.05 2.95 3 led

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